The subject matter disclosed herein relates to solutions for modeling objects in the design of integrated circuits. More specifically, the subject matter disclosed herein relates to developing a function and generating a model of spatially correlated attribute variation in an integrated circuit, and an associated design structure.
The design and manufacture of integrated circuit devices includes accounting for attribute and dimensional variations as a result of device location and various manufacturing processes (e.g., lithography, processing, etc.). Devices which in the initial design are intended to be identical, may, when actually manufactured on a chip, have variations in critical dimensions or electrical characteristics as a result of manufacturing processes and the relative positions of the devices on the chip. Design techniques which limit or control these variations can increase the size of the chip and impact the performance of those devices significantly. Generating accurate and workable models of these variations can help to reduce the size of the chip and aid in effectively designing the integrated circuit to avoid or account for these effects in advance.
Conventional approaches for evaluating and modeling these variations between devices on a chip include assigning a standard amount of independent random variation to each device on the chip, or dividing the chip into a number of sections and assigning a single random variation value to each section (and each device in that section) on the chip. However, these approaches fail to adequately account for spatial correlations in device variances, and thus, generate discontinuous models which may be inaccurate and/or lead to overdesigning.